Embodiments of the present invention relate to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device including a buried gate and a method for forming the same.
A Dynamic Random Access Memory (DRAM) includes a plurality of unit cells, each of which includes a capacitor and a transistor. The capacitor is used to temporarily store data therein. The transistor is used to transmit data from a bit line to a capacitor in correspondence with a control signal (e.g., a control signal applied to a word line) using the electric conductivity of a semiconductor device that changes depending on environment. The transistor has three regions including a gate, a source and a drain, where charges between the source and the drain move in response to a control signal applied to the gate. The charges between the source and the drain move through a channel region in accordance with the properties and operation of the semiconductor device.
When a general transistor is formed in a semiconductor substrate, a gate is formed on the semiconductor substrate, and the semiconductor substrate is doped with impurities at both sides of the gate to form a source and a drain. In this case, the region under the gate between the source and the drain acts as a channel region of the transistor. Thus, is such a case the channel region extends horizontally, and a transistor including the horizontal channel region occupies a predetermined area of a semiconductor substrate. Reducing the overall area of a complicated semiconductor memory apparatus is difficult due to the large number of transistors with horizontal channel regions that are contained in the semiconductor device.
In the manufacturing process of a semiconductor memory device, a wafer is provided on which a plural number of the semiconductor devices are formed. If the overall area of the semiconductor memory device is reduced, the number of semiconductor memory devices capable of being acquired from each wafer is increased, resulting in increased productivity. A variety of methods have been proposed to reduce the overall area of the semiconductor memory device. A representative method uses a recess gate wherein a recess is formed in a substrate and a gate is formed in the recess such that a curved channel region extends along the outer surfaces of the recess, instead of using a conventional planar gate having a horizontal channel region. Another representative method is burying the entirety of the gate in the recess to form a buried gate.
In the case of the buried gate structure, the entire gate is buried under the surface of the semiconductor substrate, so that a channel length and width can be guaranteed. With such a structure, parasitic capacitance between a gate (word line) and a bit line can be decreased by about 50% as compared to the conventional planar gate.
However, from the viewpoint of the entire structure which includes both a cell region and a peripheral region, when implementing the buried gate structure, there is a difference in height between the buried gate of the cell region a gate formed in the peripheral region; and therefore, a method for compensating for the space caused by the difference in height is necessary. A variety of methods have been considered, for example, i) one method in which a cell region space as high as the gate of the peripheral region remains empty or unused, and ii) another method in which the bit lines of the cell region are formed simultaneously with the process of forming the gate of the peripheral area.
However, the above-mentioned method (i), in which empty/unused space is provided for the cell region, has a disadvantage in that a storage node contact should be formed at a deeper depth when the height of the storage node contact plug is increased, resulting in an increased degree of difficulty in forming a bit line. The above-mentioned method (ii) for simultaneously forming the gate of the peripheral region and the gate of the cell region has a disadvantage in that an electrode of the cell region bit line and the gate electrode of the peripheral region are formed by the same material since they are formed through the same process, and thus a barrier metal layer is also formed, and consequently the gate of the peripheral region becomes higher. As a result, parasitic capacitance of the cell region increases which is contrary to the goal behind formation of the buried gate.